The present invention relates generally to data communications, and more particularly to methods and apparatus for modulating signals for transmission on a limited number of data media. Various aspects of the invention relate to modulation schemes that are particularly well suited for transmitting timing information that is associated with digital data.
High-speed digital networks are commonly used to transmit voice, data, facsimile and other information. Such networks have many uses, especially in the fields of telecommunications and supercomputing. In response to demand for high speed communications architectures, fiber optic networks and other high-bandwidth technologies have been developed. Fiber optic networks typically represent data bits as pulses of light traveling along long strands of optical fiber. Similarly, electrical networks represent data bits as electrical signals on an electrical transmission line. The pulses of light or electricity are typically grouped together into packets that can be quickly switched and relayed through complicated network systems. Other media for transmitting digital data include, for example, copper wires, microwaves, coaxial cables and radio signals.
In North America, a basic telecommunications protocol for digital communications over fiber optic networks is the synchronous optical network, or SONET. In Europe and Asia, a similar protocol known as the synchronous digital hierarchy (SDH) protocol is more prevalent. Both SONET and SDH define standards that are commonly known so that products manufactured by various companies can communicate with each other. American National Standards Institute, Inc., for example, publishes a SONET standard that specifies optical interface rates, message format specifications and the like. A common SONET standard (OC-192) generally specifies a common clock rate of about 10 GHz, with an acceptable tolerance of +/xe2x88x9220 ppm. The tolerance is necessary because clock signals are generated by many different sources in SONET networks, so some variation is generally unavoidable. SONET also defines blocks of optical communication called xe2x80x9coptical channelsxe2x80x9d (OCs). A basic optical channel (OC-1) bit rate is 51.84 Mbps (million bits per second), and each OC can be subdivided into sub-channels. Higher bit rates are frequently defined as multiples of the OC-1 bit rate. For example, a 10 Gbps (10,000,000,000 bits per second) channel could transmit as many as 192 OC-1 channels. With WDM (wavelength division multiplexing), several (4-80) OC-192 channels can be transmitted on a single fiber. One OC-192 fiber can generally transmit up to 150,000 simultaneous phone conversations. In general, the frequency of the clock signal is two times that of the xe2x80x9c10101010xe2x80x9d bit pattern with NRZ (Non-Return to Zero) data.
Typically, communications networks such as those based on the SONET standard include switching systems that are used to configure the network based upon command or network failure. Because SONET and SDH networks carry high volumes of traffic, relatively large switch fabrics are typically required. For example, common digital switches utilized (referred to as 128xc3x97128 switches) are capable of routing a signal received on any of 128 inputs to any of 128 outputs. Other preferred switch fabrics commonly used in high speed switches include 256xc3x97256 switches and 512xc3x97512 switches, among others.
At present, the most preferable switch fabrics generally require more transistors than are conveniently available on most high-speed semiconductor device technologies. The sheer volume of transistors required to implement large switch fabrics, then, generally prohibits the implementation of a large switch fabric on a single chip. It is typically very difficult, for example, to implement switches larger than 16xc3x9716 with current gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) technology. Because of this limitation, large Nxc3x97N switches are typically created by suitably interconnecting multiple switches of relatively small fabrics. Many techniques for building high-fabric switches from lower-fabric switches can be conceived, such as the exemplary 4xc3x974 switch constructed from six 2xc3x972 switches in a three-stage architecture shown in FIG. 1. With larger switches, this approach minimizes the required number of cross points. Similarly, switches on the order of 512xc3x97512, for example, can be constructed from various combinations of 4xc3x974, 8xc3x978, 16xc3x9716 or other Nxc3x97M switches.
As data passes through the various stages of a multi-stage switch, however, various imperfections in the switch generally create noise in the data. Time domain noise in such switches is frequently referred to as xe2x80x9cjitterxe2x80x9d. Stated another way, jitter is the short-term variation of a digital signal""s significant instant from an ideal position in time. In the SONET standard, jitter is generally defined as a phase oscillation of at least 10 Hz. The RMS value of random jitter over chains of N switches can typically be shown to increase in proportion to the square root of N, and pattern dependent jitter due to symbol interference tends to increase proportionally with N. If jitter becomes too high, the associated data stream may become unrecoverable without errors. The practical size of switches that can be built from combinations of smaller switches, then, is generally limited by the jitter imposed in each of the various stages.
Several schemes have been devised to eliminate jitter from digital data. One method involves recovering timing data (e.g., a clock signal) from the data itself before and/or after the data passes through the switch. The recovered clock signal is then generally used to re-time the data, typically through a decision circuit such as a flip-flop. Clock recovery circuitry typically includes relatively costly phase-locked loops (PLLs), saw filters, or the like to extract timing information. In addition to being expensive, multiple PLLs are typically difficult to implement on integrated circuits because the voltage-controlled oscillators (VCOs) required by the PLLs tend to phase lock to each other when multiple PLLs are implemented on a single IC. Moreover, PLLs are frequently unable to recover timing data from digital signals that have passed through large switch cascades because the resulting jitter makes the data signal unreadable. PLLs are sometimes implemented between the various stages of the switch to eliminate jitter in intermediate steps, but multiple PLLs compound problems of cost and complexity. Because of cost and other implementation disadvantages, PLL extraction of timing data is an imperfect method of jitter elimination.
Other methods of reducing jitter involve transmitting each data signal in conjunction with a clock signal so that the data can be retimed and recovered to remove accumulated jitter. For example, data signals and associated clock signals may be provided as separate inputs to a Nxc3x97N switch 200, as shown in FIG. 2A. Data signals and clock signals are routed through switch 200 by control logic 204. Each data signal is then re-timed based upon its own timing information by re-timer 202 which is, for example, a delay locked loop (DLL) circuit.
Alternatively, clock and data signals may be switched through separate Nxc3x97N switches as shown, for example, in FIG. 2B. In such a scheme, control logic 204 sequences data signals from multiple sources through Nxc3x97N switch 200. Corresponding clock signals extracted from the data are switched through a separate Nxc3x97N switch 200A. The clock re-synchronizes data 202, thereby removing at least some of the accumulated jitter.
Numerous variations of these methods of separately switching clock and data signals could be conceived. Each of these methods, however, generally exhibits certain marked disadvantages. Most notably, the separate switching of clock information requires significant bandwidth. Clock signals in the OC-192 SONET standard, for example, are typically on the order of 10 GHz, so the resources necessary to switch and transmit such high frequency information for every signal are significant. Moreover, the added architecture increases the expense of the switch, as well as the complexity.
A preferred embodiment of the present invention determines the differences between transmitted clock signals and a particular reference signal. For OC-192 SONET signals, the differences between the clock signals observed and a 10 GHz reference is relatively small (i.e. approximately 20 kHz). Therefore, the low bandwidth difference signals are efficiently transmitted along with the reference signal such that the receiver re-constructs the original clock signal from the difference signal and the reference signal. Because the difference signals generally require little bandwidth compared to the reference signal, many difference signals can be multiplexed together via any multiplexing technique. Thus, many clock signals can be reconstructed from a single reference signal and the multiplexed difference signals. Other embodiments of the invention may employ other multiplexing techniques and signal combination/extraction techniques.